Package structure

ABSTRACT

A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims under 35 U.S.C. §119 (a) the benefit ofTaiwanese Application No. 098145249 filed Dec. 28, 2009 the entirecontents of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to package structures, and moreparticularly, to a high-quality and low-cost package structure.

2. Description of Related Art

In a conventional lead frame based semiconductor package, such as a QFN(Quad Flat Non-lead) package, a semiconductor chip is adhered to a chipcarrier, such as a lead frame, and encapsulated by an encapsulant, andleads of the lead frame are exposed from the encapsulant to serve as I/Oconnections for electrically connecting the semiconductor chip to anexternal device, such as a printed circuit board, as disclosed by U.S.Pat. No. 5,942,794, No. 6,143,981, No. 6,229,200 and No. 6,498,099.

In addition, carrier-free packages are developed to reduce package size,as disclosed by U.S. Pat. No. 5,830,800 and No. 6,770,959. FIGS. 1A to1C show such a carrier-free package. Referring to FIG. 1A, a metal plate10 made of copper is prepared, and a plurality of electrical contactpads 11 is formed on the metal plate 10 by electroplating. Referring toFIG. 1B, a chip 12 is adhered to the metal plate 10 and electricallyconnected to the electrical contact pads 11 through bonding wires 13.Then, an encapsulant 14 is formed on the metal plate 10 to cover thechip 12 and the bonding wires 13. Referring to FIG. 1C, the metal plate10 is removed by etching such that the bottom surfaces of the electricalcontact pads 11 are exposed to serve as I/o connections for electricallyconnecting to an external device.

However, with the metal plate 10 being unfit for routing, lengthybonding wires are required, thereby increasing the cost and adverselyaffecting the electrical performance of the package.

Accordingly, U.S. Pat. No. 6,884,652 discloses a carrier-free packagethat can arrange conductive traces and shorten bonding wires so as toimprove the electrical performance of the package. FIGS. 1A′ to 1C′ showsuch a carrier-free package. Referring to FIG. 1A′, a metal plate 10made of copper is prepared, and a dielectric layer 100 is formed on themetal plate 10 to allow a plurality of openings to be formed in thedielectric layer 100 to expose portions of the metal plate 10. Referringto FIG. 1B′, a wiring layer 11′ is formed on the dielectric layer 100 bysuch as sputtering. The wiring layer 11′ comprises a plurality ofconductive traces 111, a plurality of electrical contact pads 112 andbond fingers 113 formed at two ends of the conductive traces 111,respectively. Then, a chip 12 is adhered over the dielectric layer 100and electrically connected to the bond fingers 113 through bonding wires13. Then, referring to FIG. 1C′, an encapsulant 14 is formed over thedielectric layer 100 to cover the wiring layer 11′, the chip 12 and thebonding wires 13, and a singulation process is performed. Thereafter,the metal plate 10 is removed by such as etching to expose the bottomsurfaces of the electrical contact pads 112. The exposed bottom surfacesof electrical contact pads 112 serve as I/o connections for electricallyconnecting to an external device.

However, the above-described technique incurs high costs and requirescomplicated processes and is not suitable for mass production because ofthe necessity of forming the dielectric layer 100 on the metal plate 10and forming the wiring layer 11′ by such as sputtering.

Accordingly, a semiconductor package that can arrange conductive tracesbut dispense with a dielectric layer is proposed by U.S. Pat. No.6,306,682. FIGS. 1A″ to 1D″ show the semiconductor package.

Referring to FIG. 1A″, a metal plate 10 made of copper and having afirst surface 10 a and an opposed second surface 10 b is prepared, anelectroplated metal layer 101 and an electroplated wiring layer 11′ areformed on the first surface 10 a and the opposed second surface 10 b ofthe metal plate 10, respectively. The wiring layer 11′ comprises aplurality of electrical contact pads 112. A solder mask layer 15 isfurther formed on the second surface 10 b and the wiring layer 11′. Aplurality of openings 150 is formed in the solder mask layer 15 toexpose the bottom surfaces of the electrical contact pads 112. Theexposed bottom surfaces of the electrical contact pads 112 serve as I/oconnections for electrically connecting to an external device. Referringto FIG. 1B′, the metal plate 10 is etched, from the first surface 10 aof the metal plate 10, to form an open area 101 a which penetrates themetal plate 10. As shown in FIG. 1C″, a chip 12 is received in the openarea 101 a such that the chip 12 is adhered to the solder mask layer 15and electrically connected to the electrical contact pads 112 throughbonding wires 13. Further, an encapsulant 14 is formed in the open area101 a to encapsulate the chip 12 and the bonding wires 13, and solderballs 16 are formed on the electrical contact pads 112 in the openings150. Finally, as shown in FIG. 1D″, the package is singulated along theperiphery of the open area 101 a so as to remove the metal plate 10.

However, in the above-described technique, due to the materialcharacteristics of the solder mask layer 15, it is difficult to form aneven surface on the solder mask layer 15. As such, when the chip 12 isadhered to the solder mask layer 15, a crack S can easily occur to thesolder mask layer 15 (as shown in FIGS. 1C″ and 1D″), thus reducing theproduct yield. Further, since lithography processes such as mask andexposure processes are required for forming the openings 150 in thesolder mask layer 15, it incurs high costs and precludes massproduction.

Therefore, it is imperative to overcome the above drawbacks of the priorart.

SUMMARY OF THE INVENTION

In view of the above drawbacks of the prior art, the present inventionprovides a package structure, which comprises: a base body having awiring layer and a first encapsulant, wherein the wiring layer has aplurality of conductive traces and a plurality of first electricalcontact pads, the first encaspulant has an embedding surface forembedding and exposing the wiring layer and an external surface opposedto the embedding surface and having a plurality of openings for exposingthe first electrical contact pads of the wiring layer; a chipelectrically connected to the wiring layer; and a second encapsulantformed on the embedding surface for covering the chip and the wringlayer.

In the above structure, the first encapsulant and the second encapsulantare made of a polymer material such as an epoxy resin. The wiring layeris made of at least one selected from the group consisting of gold,palladium, and nickel.

The chip is flip-chip connected to the wiring layer or electricallyconnected to the wiring layer through bonding wires electricallyconnected to a plurality of bond fingers on the wiring layer.

In an embodiment, a plurality of solder balls or conductive bumps isdisposed on the exposed first electrical contact pads, respectively. Thebase body can further have a die pad embedded beneath and exposed fromthe embedding surface, wherein the wiring layer is located at theperiphery of the die pad, and the chip is disposed on the die pad.Further, a portion of the die pad is exposed from at least one of theopenings of the first encapsulant to serve as a second electricalcontact pad such that a solder ball or conductive bump is disposedthereon.

The present invention further provides a package structure, whichcomprises: a base body having a wiring layer and a first encapsulant,wherein the wiring layer has a plurality of conductive traces and aplurality of first electrical contact pads, the first encaspulant has anembedding surface for embedding and exposing the wiring layer and anexternal surface opposed to the embedding surface and having a pluralityof first openings for exposing the first electrical contact pads of thewiring layer; a chip electrically connected to the wiring layer; aplurality of conductive posts disposed on the first electrical contactpads of the embedding surface, respectively; and a second encapsulantformed on the embedding surface for covering the chip, the wring layerand the conductive posts and having a plurality of second openings forexposing the conductive posts, respectively.

In the above structure, the first encapsulant and the second encapsulantare made of a polymer material such as an epoxy resin. The wiring layeris made of at least one selected from the group consisting of gold,palladium, and nickel.

The chip is flip-chip connected to the wiring layer or electricallyconnected to the wiring layer through bonding wires electricallyconnected to a plurality of bond fingers on the wiring layer.

Further, a plurality of solder balls or conductive bumps are disposed onthe first electrical contact pads in the first openings, respectively.The base body can further have a die pad embedded beneath and exposedfrom the embedding surface, wherein the wiring layer is located at theperiphery of the die pad, and the chip is disposed on the die pad.Further, a portion of the die pad is exposed from at least one of theopenings of the first encapsulant to serve as a second electricalcontact pad such that a solder ball or conductive bump is disposedthereon.

The conductive posts are made of copper. A plurality of third electricalcontact pads are formed on the conductive posts and exposed from thesecond openings. The third electrical contact pads are made of at leastone selected from the group consisting of gold, palladium, and nickel.

According to the present invention, the first encapsulant is formed tocover the wiring layer so as to provide an even surface. As such, whenthe chip is disposed on the first encapsulant, cracks will not occur tothe first encapsulant, thereby preventing the conventional drawbackscaused by the use of a solder mask layer and greatly improving theproduct quality.

Further, the present invention dispenses with a solder mask layer forcovering the wiring layer and accordingly does not require a lithographyprocess for forming openings in a solder mask layer, thus reducing thecost and facilitating mass production.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1C are sectional views of a conventional package structure;

FIGS. 1A′ to 1C′ are sectional views of another conventional packagestructure;

FIGS. 1A″ to 1D″ are sectional views of another conventional packagestructure;

FIGS. 2A to 2H are schematic views of a package structure according to afirst embodiment of the present invention, wherein FIG. 2B is asectional view of FIG. 2B′, and FIG. 2H′ shows another embodiment of thepackage structure depicted in FIG. 2H; and

FIGS. 3A to 3F are sectional views of a package structure according to asecond embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate thedisclosure of the present invention, these and other advantages andeffects can be apparent to those in the art after reading thisspecification.

First Embodiment

FIGS. 2A to 2H are schematic views of a package structure according to afirst embodiment of the present invention. For the purpose of brevity,only one package unit is shown in the drawings. But it should be notedthat the present invention is not limited thereto. For example, aplurality of package units arranged in array are provided in practice

Referring to FIG. 2A, a metal plate 20 having a first surface 20 a andan opposed second surface 20 b is provided, and at least an activeregion A is defined on the metal plate 20. Then, a resist layer 200 suchas photo resist is formed on the first and second surfaces 20 a, 20 b,and a plurality of patterned open areas 200 a is formed in the resistlayer 200 for exposing portions of the first and second surfaces 20 a,20 b of the metal plate 20. Further, a patterned metal layer 201 isformed in the open areas 200 a by electroplating, wherein the metallayer 201 on the first surface 20 a inside the active region A comprisesa die pad 210 and a plurality of wiring layers 21. The metal layer 201on the first and second surfaces 20 a, 20 b outside the active region Aserve as an anti-etching structure 214 in a subsequent etching process.

In the present embodiment, the metal plate 20 is made of copper, and thedie pad 210 and the wiring layers 21 are made of at least one selectedfrom the group consisting of gold, palladium, and nickel. The wiringlayers 21 each have a plurality of conductive traces 211, a plurality offirst electrical contact pads 212 and bond fingers 213 formed at twoends of the conductive traces 211, respectively, wherein the firstelectrical contact pad 212 serve as ball pads, as shown in FIG. 2B′.

Referring to FIG. 2B, there is shown a sectional view of FIG. 2B′, theresist layer 200 is removed to expose portions of the first surface 20 aand the second surface 20 b in the active region A. Referring to FIG.2B′, the wiring layers 21 are located at the periphery of the die pad210.

Referring to FIG. 2C, a first encapsulant 24 a is formed on the firstsurface 20 a to extend beyond the active region A to cover the die pad210 and the wiring layers 21, thereby embedding the die pad 210 and thewiring layers 21 in the first encapsulant 24 a. The first encapsulant 24a is of a thickness substantially between 0.1 and 0.5 mm, and is made ofan epoxy resin polymer material such as EMC (epoxy mold compound), PP(prepeg), ABF (Ajinomoto build-up film) and the like.

Referring to FIG. 2D, the metal plate 20 is etched from the secondsurface 20 b in the active region A along the edges of the anti-etchingstructure 214 so as to form an open area 202 penetrating the metal plate20, and in consequence the die pad 210 and the wiring layers 21 areexposed from the open area 202.

Referring to FIG. 2E, a chip 22 is disposed on the die pad 210 in theopen area 202 and electrically connected to the bond fingers 213 of thewiring layers 21 through a plurality of bonding wires 23.

Referring to FIG. 2F, a second encapsulant 24 b is formed on the metalplate 20 in the open area 202 to cover the chip 22, the wiring layers 21and the bonding wires 23 and extend beyond the open area 202. The secondencaspulant 24 b is made of the same material as the first encapsulant24 a, for example, EMC.

Referring to FIG. 2G, a plurality of openings 240 is formed in the firstencapsulant 24 a by drilling such that the first electrical contact pads212 are exposed from the openings 240, wherein the first electricalcontact pads 212 are of a width of about 20 μm greater than the diameterof the openings 240. Portions of the die pad 210 are selectively exposedfrom the openings 240 to serve as second electrical contact pads 215.Conductive elements 25, such as solder balls or conductive bumps, areformed on the first and second electrical contact pads 212, 215 suchthat a printed circuit board can be mounted on the conductive elements25.

Referring to FIG. 2H, the metal plate 20 is cut and removed so as toform a package structure 2.

In the present embodiment, the first encapsulant 24 a is formed to coverthe die pad 210 and the wiring layers 21 so as to provide an evensurface. As such, when the chip 22 is disposed above the firstencapsulant 24 a, cracks will not occur to the first encapsulant 24 a,thereby preventing the conventional drawbacks caused by the use of asolder mask layer and greatly improving the product quality.

Further, the present invention dispenses with a solder mask layer forcovering the die pad 210 and the wiring layers 21 and accordingly doesnot require a lithography process for forming openings in a solder masklayer, thus reducing the cost and facilitating mass production.

The present invention further provides a package structure 2,comprising: a base body 2 a having a first encapsulant 24 a, a die pad210 and a plurality of wiring layers 21; a chip 22 disposed on the basebody 2 a and electrically connected to the wiring layers 21; and asecond encapsulant 24 b formed on the base body 2 a to cover the wiringlayers 21 and the chip 22.

The wiring layers 21 of the base body 2 a are located at the peripheryof the die pad 210, and has a plurality of conductive traces 211 and aplurality of first electrical contact pads 212. The first encapsulant 24a has an embedding surface 241 and an opposed external surface 242,wherein the die pad 210 and the wiring layers 21 are embedded beneathand exposed from the embedding surface 241 of the first encapsulant 24a, and the external surface 242 of the first encapsulant 24 a has aplurality of openings 240 for exposing the first electrical contact pads212, respectively.

The die pad 210 and the wiring layers 21 are made of at least oneselected from the group consisting of gold, palladium, and nickel.Conductive elements 25, such as solder balls or conductive bumps, aredisposed on the first electrical contact pads 212 in the openings 240for electrically connecting to an external device, such as a printedcircuit board. Further, portions of the bottom surfaces of the die pad210 are exposed from the openings 240 to serve as second electricalcontact pads 215 for the mounting of conductive elements 25 thereon.

The chip 22 is mounted on the die pad 210 embedded beneath the embeddingsurface 241 and electrically connected to the wiring layers 21 throughbonding wires. Referring to FIG. 2H′, a package 2′ is shown according toanother embodiment, wherein a chip 22′ is flip-chip connected to aplurality of wiring layers 21′, thereby dispensing with the die pad.

Second Embodiment

FIGS. 3A to 3F are sectional views of a package structure according to asecond embodiment of the present invention. The second embodimentdiffers from the first embodiment in that the conductive posts 36 in thesecond embodiment are formed for facilitating a stacking process.

Referring to FIG. 3A, a metal plate 30 with a structure as shown in FIG.2C is provided, and a plurality of third electrical contact pads 301corresponding in position to the first electrical contact pads 312 isformed on the second surface 30 b in the active region A.

Referring to FIG. 3B, the metal plate 30 is etched from the secondsurface 30 b in the active region A along the inner edges of ananti-etching structure 314 and edges of the third electrical contactpads 301 so as to form an open area 302 to penetrate the metal plate 30,and in consequence the die pad 310, wiring layers 311 and bond fingers313 are exposed from the open area 302. Therein, the portions of themetal plate 30 located between the first electrical contact pads 312 andthe third electrical contact pads 301 corresponding in position theretoare shielded by the third electrical contact pads 301 and thus notetched away during the etching process to thereby form a plurality ofconductive posts 36

Referring to FIG. 3C, a chip 32 is mounted on the die pad 310 andelectrically connected to the bond fingers 313 through a plurality ofbonding wires 33; further, a second encapsulant 34 b is formed in theopen area 302 to cover the chip 32, the conductive posts 36, the wiringlayers 31, and the bonding wires 33.

Referring to FIG. 3D, a plurality of first openings 340 a is formed inthe first encapsulant 34 a by laser drilling for exposing the firstelectrical contact pads 312 and the second electrical contact pads 315.As such, conductive elements 35 can further be formed on the first andsecond electrical contact pads 312, 315 to allow a printed circuit boardto be mounted on the conductive elements 35; meanwhile, a plurality ofsecond openings 340 b is formed in the second encaspulant 34 b forexposing portions of the third electrical contact pads 301 on theconductive posts 36.

Referring to FIG. 3E, the metal plate 30 is cut and removed to form apackage structure 3.

Referring to FIG. 3F, another package structure 3′ is stacked on theconductive posts 36 via the conductive elements 35′ thereof.

The present invention further provides a package structure 3,comprising: a base body 3 a having a first encapsulant 34 a, a die pad310 and a plurality of wiring layers 31; a chip 32 and a plurality ofconductive posts 36 disposed on the base body 3 a and electricallyconnected to the wiring layers 31; and a second encapsulant 34 b formedon the base body 3 a to cover the wiring layers 31, the chip 32, and theconductive posts 36.

The wiring layers 31 of the base body 3 a are located at the peripheryof the die pad 310, and has a plurality of conductive traces 311 and aplurality of first electrical contact pads 312. The first encapsulant 34a has an embedding surface 341 and an opposed external surface 342defined thereon. The die pad 310 and the wiring layers 31 are embeddedbeneath and exposed from the embedding surface 341 of the firstencapsulant 34 a. The external surface 342 has a plurality of firstopenings 340 a for exposing the first electrical contact pads 312.

The die pad 310 and the wiring layers 31 are made of at least oneselected from the group consisting of gold, palladium, and nickel.Conductive elements 35, such as solder balls or conductive bumps, aredisposed on the first electrical contact pads 312 in the first openings340 a for electrically connecting to an external device, such as aprinted circuit board. Further, portions of the bottom surfaces of thedie pad 310 are exposed from the first openings 340 a to serve as thesecond electrical contact pads 315 for the mounting of conductiveelements 35 thereon.

The chip 32 is mounted on the die pad 310 embedded beneath the embeddingsurface 341 and electrically connected to the wiring layers 31. In anembodiment, the wiring layers 31 comprise the bond fingers 313, and thechip 32 is electrically connected to the bond fingers 313 of the wiringlayers 31 through bonding wires 33. Alternatively, the chip 32 isflip-chip connected to the wiring layers 31.

The second encapsulant 34 b is formed on the embedding surface 341 andhas a plurality of second openings 340 b for exposing the top surface ofthe conductive posts 36. The second encapsulant 34 b is made of the samematerial as the first encapsulant 34 a, such as EMC.

The conductive posts 36 are disposed on the first electrical contactpads 312 embedded beneath the embedding surface 341 for bonding withconductive elements 35′, such as solder balls or conductive bumps, toallow another device, such as another package structure 3′, to bemounted on the conductive elements 35′. The conductive posts 36 are madeof copper and configured for electrical conduction. The conductive posts36 further have third electrical contact pads 301 formed thereon andexposed from the second openings 340 b, respectively. The thirdelectrical contact pads 301 are made of at least one selected from thegroup consisting of gold, palladium, and nickel.

According to the present invention, the first encapsulant is formed tocover the wiring layers so as to provide an even surface thereof. Assuch, when the chip is disposed on the first encapsulant, cracks willnot occur to the first encapsulant, thereby greatly improving theproduct quality.

Further, the present invention dispenses with a solder mask layer forcovering the die pad and the wiring layers and accordingly does notrequire a lithography process for forming openings in a solder masklayer, thus reducing the cost and facilitating mass production.

The above-described descriptions of the specific embodiments areintended to illustrate the preferred implementation according to thepresent invention but are not intended to limit the scope of the presentinvention, Accordingly, all modifications and variations completed bythose with ordinary skill in the art should fall within the scope ofpresent invention defined by the appended claims.

What is claimed is:
 1. A package structure, comprising: a base bodycomprising a wiring layer and a first encapsulant, wherein the wiringlayer has a plurality of conductive traces, a plurality of firstelectrical contact pads, and a plurality of bond fingers, the firstencapsulant has an embedding surface for embedding and exposing thewiring layer and an external surface opposed to the embedding surface,the embedding surface is flush with a surface of the conductive traces,the external surface covers the conductive traces, the first electricalcontact pads and the bond fingers, the external surface is formed with aplurality of openings for exposing the first electrical contact pads,and the bond fingers are free from being exposed from the externalsurface; a chip disposed on the embedding surface of the firstencapsulant and electrically connected to the bond fingers of the wiringlayer; and a second encapsulant formed on the embedding surface of thefirst encapsulant for covering the chip and the wiring layer.
 2. Thestructure of claim 1, wherein the first encapsulant is made of one ofEMC (epoxy mold compound), PP (prepeg), and ABF (Ajinomoto build-upfilm).
 3. The structure of claim 1, wherein the second encapsulant ismade of one of EMC, PP and ABF.
 4. The structure of claim 1, wherein thewiring layer is made of at least one selected from the group consistingof gold, palladium, and nickel.
 5. The structure of claim 1, wherein thechip is electrically connected to the wiring layer through bonding wirescovered with the second encapsulant.
 6. The structure of claim 1,wherein a plurality of solder balls or conductive bumps is disposed onthe exposed first electrical contact pads, respectively.
 7. Thestructure of claim 1, wherein the base body further has a die padembedded beneath and exposed from the embedding surface, the wiringlayer being located at a periphery of the die pad, and the chip beingmounted on the die pad.
 8. The structure of claim 5, wherein the bondfingers are electrically connected to the bonding wires.
 9. Thestructure of claim 7, wherein a portion of the die pad is exposed fromat least one of the openings of the first encapsulant to serve as asecond electrical contact pad, and a solder ball or conductive bump isdisposed on the second electrical contact pad.
 10. A package structure,comprising: a base body comprising a wiring layer and a firstencapsulant, wherein the wiring layer has a plurality of conductivetraces, a plurality of first electrical contact pads, and a plurality ofbond fingers, the first encapsulant has an embedding surface forembedding and exposing the wiring layer and an external surface opposedto the embedding surface, the embedding surface is flush with a surfaceof the conductive traces and having a plurality of first openings forexposing the first electrical contact pads of the wiring layer; a chipdisposed on the embedding surface of the first encapsulant andelectrically connected to the bond fingers of the wiring layer; aplurality of conductive posts disposed on the first electrical contactpads embedded beneath the embedding surface, respectively; and a secondencapsulant formed on the embedding surface for covering the chip, thewring layer and the conductive posts and having a plurality of secondopenings for exposing the conductive posts, respectively.
 11. Thestructure of claim 10, wherein the first enbapsulant is made of one ofEMC, PP, and ABF.
 12. The structure of claim 10, wherein the secondenbapsulant is made of one of EMC, PP and ABF.
 13. The structure ofclaim 10, wherein the wiring layer is made of at least one selected fromthe group consisting of gold, palladium, and nickel.
 14. The structureof claim 10, wherein the chip is electrically connected to the wiringlayer through bonding wires covered with the second encapsulant.
 15. Thestructure of claim 10, wherein a plurality of solder balls or conductivebumps is disposed on the first electrical contact pads in the firstopenings, respectively.
 16. The structure of claim 10, wherein the basebody further has a die pad embedded beneath and exposed from theembedding surface, the wiring layer being located at a periphery of thedie pad, and the chip being mounted on the die pad.
 17. The structure ofclaim 10, wherein a plurality of solder balls or conductive bumps isdisposed on the conductive posts in the second openings, respectively.18. The structure of claim 10, wherein the conductive posts are made ofcopper.
 19. The structure of claim 10, wherein a plurality of thirdelectrical contact pads are formed on the conductive posts and exposedfrom the second openings, respectively.
 20. The structure of claim 14,wherein the wiring layer has the plurality of bond fingers electricallyconnected to the bonding wires.
 21. The structure of claim 16, wherein aportion of the die pad is exposed from at least one of the openings ofthe first encapsulant to serve as a second electrical contact pad so asfor a solder ball or conductive bump to be disposed on the secondelectrical contact pad.
 22. The structure of claim 19, wherein the thirdelectrical contact pads are made of at least one selected from the groupconsisting of gold, palladium, and nickel.